Samuel A. Falvo IISometimes, I get burned out by the hardware aspect of the project. When this happens, I often wonder to myself, "Man, if only I had the Kestrel *finished*, then I can work on the software." I reached that point not too long ago.
So, I worked on developing a new emulator for the new Kestrel-3 hardware design. It only supports the headless configuration right now (CPU module only; no I/O module). As part of this, I also ported DX-Forth to the emulated environment. Presently, DX-Forth boots and runs, but it has no secondary storage support.
It's not committed to the repository yet, but will be landing soon.
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This is good - I'm a great believer in emulation as part of development. Even emulation-first, if that's appropriate.
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You know me; I'm a big believer of test-driven development. I'm a huge fan of writing the tests first, then the production code to make those tests pass second.
However, I've had, on two separate occasions, emulators for the Kestrel which has diverged so far from reality that they ended up becoming worthless to me. The first emulator for the Kestrel-2 bears closer relationship with my end-goal for the Kestrel-3 than it ever did to the Kestrel-2 or -2DX. The first emulator for the Kestrel-3 was closer to the Kestrel-2DX in practice, but it still failed to reflect reality. It was, in fact, intended to model the Digilent Nexys-2 board's resources, none of which I could ever get to successfully work in actual hardware.
THIS emulator is not intended to reflect anything more than the raw CPU card of the latest Kestrel-3 design, and it's sole function within that scope is, literally, to help me refine what registers and bit layout I need to implement in the SIA core with DX-Forth in mind. That's literally as far as things go.
The source of truth is the hardware. The emulator is just a modeling tool towards that end. I'm so done spending appreciable amounts of time writing an emulator for a system I cannot elaborate in hardware. :-)
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I've seen the same thing happen in my professional life, in the life of a new CPU - among the early models might be a cycle-accurate or bus-activity-accurate model, which can be very useful, but there comes a time where it's not longer maintained. That's OK, if it served a purpose, and if the divergence is understood by those who might try to use it. These models are a great deal cheaper and much earlier than the HDL.
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