After some considerations, and some calculations, and mind-experiments, I've decided to just stick with a 5-stage pipeline design. Decoding RISC-V into MISC instructions is certainly possible, and possibly might even use comparable numbers of LUTs and DFFs; however, it would require a 5-read-5-write register file design, which is more complex than your usual 2-read-1-write design for single-issue, in-order pipeline designs.

Oh well. It was worth some thought!

That said, on the flight home last night, I managed to get a significant portion of the RV32I instruction set decoded in a "decode stage" of a 5-stage pipeline. This includes conditional branches, loads, stores, register- and immediate-type ALU operations. Nothing else is decoded yet though, and illegal instructions are not detected.

The operating assumption is that the "execute" stage is just the ALU, and the "writeback" stage is just the register file. I have simple implementations for these stages already, as a part of an earlier design attempt at making a 5-stage pipe.

Things yet to get working include, but is not limited to, the following:

• The entire Memory stage. This couples the CPU to the data memory, and stalls the pipeline if the addressed slave isn't fast enough to keep up.
• Exceptions and interrupts. This includes external interrupts as well as the ability to execute ECALL, EBREAK, and illegal instructions.
• RV64I extensions.
• Extending the ALU's operation to support SEQ, SNE, SGE, and SGEU comparison operations.
• LUI, AUIPC, JAL, JALR, FENCE, CSRRW, CSRRWI, CSRRS, CSRRSI, CSRRC, CSRRCI, WFI, and ERET instructions.
• Result forwarding to reduce unnecessary pipeline bubbles.
• Pipeline stall logic.
• Pipeline flush logic to support FENCE and conditional branches.

This seems like an awful lot of work, and it is admittedly non-trivial. However, only a few items on this list scare me. Most of this work seems like it ought to be easy to get working.