Agenda.

1. Kestrel Project Health.
2. CPU Plans.

Kestrel Project Health. Just wanted to keep everyone up to date with my progress, which is to say, just to let everyone know that I'm still alive. I've not had any progress recently due to a perfect storm of health issues, work, and family obligations.

Because of so many interruptions in my life at present, I've utterly given up on getting something working by the next RISC-V workshop. It's just not going to happen. The Kestrel CPU will be done "when it's done."

Polaris CPU Plans. I am thinking of starting the CPU design over from scratch, yet again. Hey, at least I'm homing in on a design I'm actually happy with! Using SMG and what I already have developed so far, I think starting the CPU over from scratch might be the best thing.

I am trying to work through a design which I wrote using SMG almost a month ago, primarily to see what it'd be like using SMG in my development process. I'm pretty pleased with the result; however, there are a lot of undefined signals and such as a result of human error. Between the size of the design and some much needed functionality in SMG itself, I find the design is too big to debug by hand after the fact. [i]SMG is so simple to use and express a design in, you're tempted to just let the design flow in a single session.[/i] [b]Resist this urge.[/b] A better notation is nice, but it's still programming. Treat the process and the tool with respect.

My thoughts are that if I just [i]freeze[/i] what I currently have, start over from scratch and incrementally build the processor up one logical facility at a time, I will have a better chance of spotting errors in my overall thinking, to say nothing of better motivation due to more frequent wins (even if each individual win is smaller as a result).