Going into this project, my vhdl experience consisted of code that made an led blink on my minispartan6+ dev board. With several youtube videos and a very useful book (Free Range VHDL), my skills quickly improved. The thing that frustrated me the most was the occasionally cryptic error messages that the Xilinx ISE Design Suite spat out. Oftentimes a mistake in one source file would lead to an error in another source file that used the original file, or an error in a file that used the file that used the original file. Anyway, I started the build with an ALU and instruction decoder; pretty much everything else stays similar even when the instruction set changes (I changed mine several times to allow for more functionality and an increased amount of registers). For the coding style of the project I used a mixture of behavioral (mostly for memory/registers), dataflow (for subcomponents), and structural (for the larger components). My intention of this project was more to learn about VHDL, and less to build a fast processor (duh...why would you build a slow, wheezing machine on a board that costs 5x as much as an MCU that can run circles around a soft processor), so the combination of styles is not likely very efficient. It was really cool to synthesize my code and view the RTL schematic that the synthesizer generated.