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Sign and Zero Flags

A project log for BREDSAC

Electronic Dynamic Storage Breadboard Computer

gregewinggreg.ewing 06/18/2018 at 12:570 Comments

A small revision

While thinking about the features below, I realised that I needed separate signals indicating the most significant word of an operation and  forcing the memory address to be odd, so I renamed the signal I was previously calling MSW to ODD, and added a new MSW signal.

Sign and Zero Flags

There are two more things we will want the ALU to do for us, and that is to provide outputs indicating the sign of a result, and whether the result was negative. The revised ALU subcircuit below implements these.

The Sign FF captures the sign bit, which is bit 16 of the most significant short word of the result. The sign bit is also replicated into the most significant bit of the result, thereby sign-extending it from 17 to 18 bits (or from 35 to 36 bits for a long word). The extra bit is usually ignored, but will play a role in multiplication later.

The Zero FF keeps track of whether thre are any non-zero bits in the result. It is set equal to the result during T0 of the least significant word, and then set to 1 if any 1 bit occurs thereafter. At the end of the operation, its complement becomes the ZERO output of the ALU.

There are two new control inputs to the ALU. LSW is activated during the least significant word of an operation, and MSW during the most significant word. For a short word operation, both are activated.

Microcode

Here is the revised microcode for the Add instructions.

# OPCODE L STAT : FETCH MASEL SHS EOI RFA1 WRF1 XSEL YSEL CMX AND CY1 CYP ODD MSW LSW

# A - Add
   11100 0 0001 :   0     1    0   1   110   1   01   10   0   0   0   0   0   1   1

   11100 1 0001 :   0     1    0   0   010   1   01   10   0   0   0   0   0   0   1
   11100 1 0010 :   0     1    0   1   110   1   01   10   0   0   0   1   1   1   0

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