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Putting together a chip level schematic ...

A project log for C61

A 6-bit 2-stage pipelined RISC CPU that fits on a single page

julianJulian 06/30/2018 at 00:190 Comments

I wasn't really sure what software to use to do the schematic, though.  Historically, I've tended to use OrCAD (I have an ancient version of it, but it does the job for most things I want to do, still), but  I decided I wanted to do this project with free software if I could.

So I played with both gEDA and Kicad.  I like Kicad better, but I can't say I'm a fan of its PCB autorouting ... it can't seem to cope with the complexity of routing signals to the TQFP100 package of the CPLD I plan on putting the register banks in.  It's possible I may need to rework the pin layout to help it: I've tried to order the pins logically, but that's ended up with the register selection inputs for bank 0 and 1 being on the same side of the chip in the same sequence ... but they need to be connected to each other and that means each line needs to cross the others, which is creating a bit of trouble.  Perhaps if I put bank 1 with a mirrored order it might work better. 

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