documenting a reverse-engineering attempt
Already have an account? Log in.
To make the experience fit your profile, pick a username and tell us what interests you.
This module has 1 Xilinx CPLD chip XC2C256 (256 macro-cells CoolRunner-II) and 4 memory chips GS8161Z18BGD-200 (1M x 18 18Mb Pipelined and Flow Through Synchronous NBT SRAM), so it's programmable logic with 8 MB of static random access memory (with parity bits) and some kind of connectors (2 x 60 pins - MIPI60pin?). Also it looks like PCB is having more than 2 layers of copper. This is all that I know about this board at this moment :)
XILINX_CPLD.pdfXC2C256 CoolRunner-II CPLD with 256 macro-cellsAdobe Portable Document Format - 303.09 kB - 11/18/2018 at 04:31 |
|
|
GSI_SRAM.pdfGS8161Z18BGD-200 - 1M x 18 18Mb Pipelined and Flow Through Synchronous NBT SRAM (5ns pipeline cycle and 6.5ns flow through cycle)Adobe Portable Document Format - 668.22 kB - 11/18/2018 at 04:31 |
|
|
Any trace on google about the manufacturer or the product ?
Nothing about this specific board PROD096A
About manufacturer - most likely it's PRO DESIGN Electronic GmbH (guess is based on sticker on the back), but their web-site doesn't have info about this relatively old board
SHAOS
Platinenmacher
Shiela Dixon
Yuri
bobricius
Let's see: CPLD and a bunch of fast memory... it could be ... literally anything depending on the bitstream. But looks like fun when you figure out how to program it and access the memory.