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A project log for Hardware MPP Tracking

A Method for Hardware Based Maximum Power Point Tracking

brian-cornellBrian Cornell 04/22/2022 at 19:380 Comments

I developed this idea while finishing work on the DC-converter section of my Solar Charger project. I needed an MPP algorithm for the firmware and didn't want to adapt the work that I had previously done with my Prototype MPP Charger - too slow. But, like that prototype, the Solar Charger's converter also uses an 8-bit PIC running at a measly 4MHz which will make any form of a P&O algorithm too slow.

What if - instead of scanning for maximum power - the array's MPP voltage is maintained by the converter? For most PV panels, the MPP voltage does not vary significantly over temperature or load.

No scanning required! The converter's impedance is limited to maintain the MPP panel/array voltage. This is incredibly easy to do, even on an 8-bit PIC, and requires just 28 lines of simple C code. Here's the snippet:

The speed of this loop is controlled by a timer which is adjusted based on how far the converter's input voltage is from the MPP value. The converter's impedance is controlled by limiting the maximum duty cycle that the hardware control loop (to regulate the output) can demand. The two loops oppose one another but operate in tandem on the converter to form a closed loop. Note that in this implementation the MPP value is actually a range and not a singular value.

This method has proven much more effective than my prior implementations using P&O algorithms, but it is still too slow (it is executing on the order of 100's of mS to a second or two). The result is that the input voltage (e.g. array Z) still crashes during load transients or partial shading conditions (but recovery is much faster).

The variant pictured above executes in the foreground and there is room to go faster. This is ultimately governed by the speed of the infinite (I call it the RUN) loop, which would move its cut-off frequency to ~200-300Hz. You could go even faster by moving it to the background (ISR), limited only by processor speed and stable execution of other controller functions. With a faster processor, hardware equivalent performance may be achieved.

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