Close
0%
0%

RC2014 Wiznet 5300

Or "prehistory meets the internet"

Public Chat
Similar projects worth following
This is a fairly simple adapter for the W830MJ to connect it to the RC2014 bus. It's a bit fast and loose with the rules but it works - for me anyway.

The WizNet 830MJ contains pretty much everything we need apart from a small amount of chip select logic on a single carrier board.

The RC2014 interface is extremely simple. A 74HCT138 generates a base chip select signal, a 74HCT32 qualifies the read/write signals to the WIZ830MJ and an LD1117 generates 3.3v to supply the WizNET.

The I/O interfaces are 5v tolerant so the only remaining issues to deal with are the timing, the reset and the voltage shifting. The reset relies upon the RC2014 backplane reset, which usually works but isn't perfect - it would be good to add a proper reset control. The timing is managed by using the W5300's ability to extend the usual 7ns data hold time. As that's in a writeable register we can write the hold timing even when read isn't working properly.

The voltage shifting is done by ignoring the problem. The low from the WizNET is near enough 0 and the high is near enough 3.3v. The RC2014 backplane runs HCT parts and the Z80 CPU expects TTL signal levels with a Vih of 2.2v so it all just works.

With some of the other processors level shifting would be needed - the 65C816 and friends for example would need level shifting on the data lines when reading.

wiznet.zip

Kicad files

Zip Archive - 57.77 kB - 08/04/2021 at 17:17

Download

wiz830mj.zip

Gerbers

Zip Archive - 79.34 kB - 08/04/2021 at 17:16

Download

wiznet830mj-use138.pdf

Schematic in PDF

Adobe Portable Document Format - 43.55 kB - 08/04/2021 at 17:16

Preview
Download

View project log

Enjoy this project?

Share

Discussions

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates