• Project log 17122022

    Quang Tran Vinh • 12/18/2022 at 05:10 • 0 comments

    [Project log 17122022] The project continues to design the UART part for the monitoring module, each chip has 16 channels, corresponding to the design that can be connected to 16 nodes, the design of the schematic diagram of node 8 done, the connections to the Nifgo development board are done.
    The next work will start to design the trace for actual testing.
    Continue to update...