Most of the I/O for this machine was covered in the previous log. Next up is the Omniport and the system latches.

The Omniport

The Omniport is the 8-bit bidirectional bus that MCM computers use to talk to their peripherals - printers, disk drives, RS232 interfaces and so on. There are eight data bits and six control bits. In operation, the MCM computer is always in full control of the Omniport and the peripherals simply respond to commands from the computer; the peripherals never initiate anything in terms of what happens on the Omniport.

The logic to implement the Omniport is pretty straightforward and is shown HERE. All the signals on the Omniport are active low. When nothing is happening on the data portion of the bus resistor network RN10 keeps the data lines high, that is, idle. U44, the GAL at the top of the diagram, orchestrates things; you can see the equations for the GAL HERE. When it's time for the CPU to send data to the Omniport the data is latched at U48 and U47 is enabled. U47 is open collector so it can pull low but it can't source. Thus all lines are pulled high by RN10 except for those pulled low by U47. When it comes time for the CPU to read data from the Omniport, U49 is enabled which gates data from the Omniport onto the data bus.

So the logic is straightforward, but getting the correct timing for the control signals was not. I was fortunate to have a copy of the Omniport specification, a relic of my days at MCM, so I knew what was required. GAL U44 looks after the generation of the control signals. To do this it users the GATE0 and GATE1 signals which come from GAL U38 and D-flip-flops U45 both of which are on the main I/O schematic HERE. There are two types of control signals:

AOS (address out strobe), COS (command out strobe) and DOS (data out strobe) put data on the Omniport for use by the peripheral. GSI (gate status in) and GDI (gate data in) read data placed on the Omniport by the peripheral. These control signals are the result of I/O instructions executed by the code.

The System Latches

The MCM/70 CPU needed to be able to receive a signal from the power supply saying that AC power had failed and it was now running from the battery, which was six "D-cell size" lead-acid cells. The machine was power hungry enough that the battery would keep it running long enough to save the content of RAM to tape, but not more. In addition the CPU needed to be able to send a signal to the power supply telling it to shut off. Thus on Rack8 there is an 8-bit input latch (U50) and an 8-bit output latch (U51), both on the main I/O schematic HERE.