Stackup

The board is comprised of 6 layers, using the following stackup:

Where L2 and L5 are solid ground layers. It is important for good signal integrity and EMC to have solid ground planes next to each power and signal layers. The stackup was chosen to respect such a constraint and maximize the number of power layers (which are parallelized for higher current carrying capacity).

Layout

Layer 1

The first layer is mostly comprised of signals, and is the only impedance-controlled layer. Impedance control is not strictly necessary in the scope of this project, but we decided to use 100-ohm controlled impedance for the RS422 and CAN interfaces. 100-ohm was chosen instead of 120-ohm for CAN because of manufacturing capabilities (120-ohm would require track width/spacing that would increase the price).

Initially, I tried to place the CAN transceiver and termination resistors as close as possible to the connector to reduce the length of the stub. In the end, I decided to place them just below where I believe are the large ground return paths, to avoid ground shifts on digital lines. Before the transceiver, the CAN lines are in the form of a differential signal, which means that they should be quite resistant to common-mode noise.

The gate drive signals were routed to minimize inductance; short and wide tracks, with the associated return path close to it. In the case of the high-side drive signal, the return path is referenced to the drain of the high-side FET. Ideally, the gate drive signals should be routed in internal layers to reduce potential noise radiating outside of the board. However, to keep them from splitting the +VBAT polygon (in pink), I decided to route them on the outer layers.

A high clearance is kept throughout the board according to IEC60664-1 where possible. 

Optional RC snubbers are placed close to the FETs to reduce ringing during switching. A further log will discuss its impact on the phases' PWM signal waveform.

An interesting thing to note is the top part, which can be broken off if a more compact footprint is desired. It is then possible to solder wires for power and CAN.

Layer 3

The first inner layer is dedicated to analog signals and a few power planes. special care was taken to route the kelvin sense connection as far as possible from noisy signals. They are surrounded on both adjacent layers by a solid ground plane, and no return currents from any layer are present in the ground planes above and below the kelvin traces.

Layer 4

Special care was taken in the layout of layers 3 and 4. As can be seen on the pictures, no signals ever cross each other on these two layers. This was done to avoid any potential crosstalk between these layers, as the dielectric thickness is quite thin (only 0.18mm, which is thinner than the space between L2-L3 or L4-L5).

Layer 6

The 6th layer is dedicated to positioning sensors, bulk capacitors, power regulators and a few other interfaces (thermistor and fan).

You might wonder why we use two magnetic encoders on the board. This is because our initial QDD actuator uses a very clever mechanism for disambiguating the position of the output after the reduction. Without a second sensor, there is an ambiguity in position after a reduction. 

To solve this issue, our first iteration of actuators uses a back-driven reduction with the same factor as the load-bearing reducer, which rotates a second magnet above the second encoder. This is then used to disambiguate the output in a very compact format, but doesn't allow for backlash estimation, as we are not measuring the real position at the output.

Our second generation of actuators uses another mechanism which might be further discussed here or in another project page. Stay tuned!