I assumed address decoding will use EEPROMs. I mean, I will need to decode the 8-bit source and destination addresses into read and write lines. I hope I could find a 256x16 or 256x32 EEPROM, but this is by far too small for these days. I have found the AT28C64B EEPROM, but it is 8K x 8. That's 12 address bits (4 extra). And only 8 bits out. And it's an active device. Unfortunately Atmel doesn't have a 16-bit output EEPROM. I'm not sure how many of these I will need until I'm mostly done with the design, but it's my current plan.

I'd prefer not to drop to a PLD or PLA. It feels a little like cheating even though these chips existed in the 80s. Not that there is a big difference in these vs. an EEPROM for address decoding. I'll think on it more.

It's just so easy in an FPGA: loadAluA <= '0' when dstAddr=x"3F" else '1';