Today I finished writing the new disassembler :-)

The assembler will follow, but for now I look at the results and effects of the opcode re-organisation which has broken quite a few things...

The disassembler is deliciously simple and small, with about 100 LOC, thanks to a few well-defined constant tables. Less code means less bugs and corner cases !

I realise that OVL has two encodings because I forgot to take bit 11 into account. There are 2 ways to encode OVL 00h. I don't see the point in adding a 9th address bit. So maybe later an overlay instruction will take a register argument. You never know. But the encoding space is here.

The destination (SND field) is now the last argument in the line, with the optional condition at the very last position. Yes I keep changing syntax rules but this time it fits the instruction format :-)

I have defined 4 opcodes for bit shuffling : SA, SH, RO, RC. These lousy names should and will change in the future...

The assembler will be significantly more complex but I'm confident and I already have the disassembler to cross-test the tools.