I'm now almost done with the first revision of this project. I intend to continue to extend the language (I've already extended the specification; I just need to implement it) so that it actually achieves my goal of being more beginner friendly while still maintaining some amount of versatility and structure.

Most of the code generation (the part I most recently finished, which takes a syntax tree and actually generates code in the target language: VHDL) was quite easy to implement; I simply traversed the parse tree and concatenated the strings in each node, adding some of VHDL's syntax in here and there. It was easy because a lot of my language is structured the same way as VHDL, so even though I'm doing the whole "parse it into a tree and generate a string from the tree" thing, I could just be doing string replacement. However, some aspects of my language (like direct connections between subcomponent ports), aren't directly translatable into VHDL. For this, I just compile a dictionary of all of the input and output ports that are used in signal assignments in the CDL program, and then create signal aliases for the ports, replacing (in the CDL source code's parse tree) the identifiers for the ports with their aliases. For the port mapping stage of VHDL component instantiation, I then just direct the port to its signal alias and voila, I'm done.

Next, I need to deal with multi-file projects and dependencies. With CDL's specification, there is no subcomponent declaration, only instantiation. In order to generate VHDL with component declaration, I need to retrieve information from another source file that has the component's generic and port definitions. I may simplify things for the purposes of just getting the first revision done by requiring that all component definitions that are dependents are in the same file as their supercomponent.

Finally, I need to handle the issue of types. I've dramatically reduced the number of types offered, and plan to change the way that arithmetic operations work on different types (e.g. addition of bit vectors is the same for signed and unsigned vectors --- in fact, I don't even have signed and unsigned bit vectors). Because of this, my type system is not directly translatable to VHDL. This will probably be the most difficult part of development of the code generator (I'm not really sure where I'm gonna start at this point), but I think once I figure out what to do, it shouldn't take very long.