It's been a while; but I have been debugging the design as time permits. Upon initial assembly using a hotskillet reflow in the garage; I had some issues with the Edison high-density connectors. After getting that sorted; the USB hub and PATA chip identified themselves to my netbook. putting a USB memory stick on the DD[4] interface of the hub showed that I could read/write the USB bus.

The USB hub is seen by the Edison in "host mode" and by J16 (host computer) in device mode. I can download Arduino sketches via J16 when in device mode.

Initial debug showed several issues.

1) the PL2571B USB->SATA chip wasn't being seen on the USB hub. Later tracked down to a bad solder joint on the clock generator's RE17 22ohm series resistor. After fixing that; the SATA interface shows up as USB Mass Storage. I do not currently have my SSD available at my home work bench; so will retrieve it from the initial test bed tomorrow.

2) the Cypress AT2LP (USB->PATA) chip is being seen on the usb bus; but because I didn't wire in an EEPROM. :(

3) U36 was the wrong package; so I can't power J16 when in host mode.

4) The U5/UE6/UE7 eeprom connections don't work because there doesn't appear to be enough bandwidth in UE6 - a risk I took in the initial design; but in retrospect was flawed to begin with.

5) J3 - the FTDI USB debug interface to the Edison kernel had some solderablity issues around J3 - I think due to close proximity to un-tented vias near the pins of J3. Was able to workaround the issue using some detail soldering - but will need to be fixed in the final design with tenting of vias - and possibly moving some of them.

I'm going to try and find the right package for U36 and more importantly figure out how to dead-bug rework a EEPROM to the AT2LP to see if I can get that interface online in the near future.

The other thing which needs to be done; but is likely beyond my home workbench capabilities is to do a USB dataeye analysis to see if there is any margin in the design.