I was going to get to work on the Sum gate (addition of two trits) but I got distracted by latches, the most elementary possible memory device. I didn't expect something as basic as a ternary equivalent to the SR latch to be too much of a challenge, but I was very sadly mistaken. Take the lowly binary SR Latch.

Being binary, it must have two steady states. In one state, only the set pin will change it. In the other state, only the reset pin will change it. And it must have a third input state wherein no change occurs. Further, it has two outputs which are always compliments of each other.

Extending this to a ternary framework has cracked my brains. At first, I tried simply hooking up two ternary NOR gates as shown in the picture. This failed... I think. The fact is, because you have to take into account the state of the inputs (2 inputs or 3?) and the current state and next state of the Q and !Q outputs... or should there be three. Depending on how you look at it, a simple latch might have anywhere from 27 to 243 possible states. I think. Also, even if you did an exhaustive test of all possible states (I actually tried) you would end up with suspect results. Any circuit that employs multiple feedback routes can potentially have race conditions. How to know if you are measuring and recording a result that will be repeatable, or one which just happened to exit the race condition in that state?

I think I need to go back to the drawing board and see just how simplified a latching feedback circuit can get and then approach that circuit with ternary signals. Just what is the ultimate simplified memory circuit?