Finally! I have built and tested a fully functional true ternary SR Latch. No more cheating with sample-and-hold circuits. The basics are as one would expect. There are two inputs, Set and Reset. In this incarnation there is only one output, Q but adding a Q complement is as trivial as tapping Q with an inverter. The design uses two comparators operating as latches between + and - with a hysteresis zone between roughly -1V and 1V. One of the two latches is passed through a C gate(clamp down, - becomes -, 0 becomes 0, and + becomes 0). These outputs are then Maxed together to give a winner-takes-all final output Q. Because of the hysteresis, a 0 input results in no change. There is encoding logic in front of the two latches such that if the Set input is - then both latches are - and the output is -. If set is + then both output + (but one is clamped down to 0, important later, but the + output still wins the winner-take-all final stage). If the Set input is 0, there is no change. The Set input can change the output from any state to + or - and can even switch between them without requiring a reset. The Reset input sits at - (logically asserting no reset) generally but bringing it to + causes the un-clamped latch to go to - while the clamped latch goes to +, which is then clamped down to 0. It is now the higher of the two and the final output is 0.

Like any latch it starts in an undefined state and needs to be initialized by giving it a reset. Valid inputs are:

Set= 0 , Reset = -, Q = Q

Set = 0, Reset = +, Q = 0

Set = -, Reset = -, Q = -

Set = +, Reset = -, Q = +

I don't list any valid states for Reset = 0 because reset should logically always be asserted one way or the other. A 0 input on the reset line is invalid in this implementation because it was easier to build up a circuit with a truth table where I could simply ignore that condition. I'll post a schematic as soon as I have time to draw one. It's actually not terribly complex and only requires four chips and a bunch of resistors and diodes. One of those chips is actually just a voltage follower to provide isolation between the open collector outputs of the encoding logic and the latches which use voltage dividers to provide hysteresis. The open collector pull-up resistors mess with the voltage dividers and skew the hysteresis zone (near as I can tell). If I move the encoding logic over to components that use push-pull outputs I may be able to bring it down to only three chips.

Next step, a true Flip-Flap-Flop which would require an enable/clock input. This should be trivial.