Success! I took the ternary SR latch and have converted it into a clocked D-Latch; a real Flip-Flap-Flop. The back end remains the same, two latches spanning - and + with a hysteresis zone between -1V and +1V. One latch passes through a C gate so it's + output is latched down to 0 and the two latches are Maxed together for the final output. The front end has been replaced with a single input that goes into a K gate (- - +) and a V gate (- + +). The K gate goes to the unclamped latch and the V gate goes to the clamped latch. In between the two input gates and the latches is an analog switch (internally just some pass-transistors) which disconnects the inputs from the latches unless an input pin is brought low (0 or -). That pin serves as the Enable/Clock input and when it is low it connects the D input to the latches through the K and V gates. When the Enable/Clock input is high there is a high-z between them and a couple of pull-middle resistors keeps the latches in the hysteresis zone so that they keep the last input they had. The K and V gates are appropriate to ensure that the D input causes the latches to assume those states that correspond to -, 0, and + after being Maxed together. Like any flip-flop, it needs to be initialized with a value because its output on power-up is unknowable.

I switched to a TLC3704 Quad Comparator for the K and V gates. It is less versatile than the the LM319 but it can do K and V and it has the benefit of using less connections and having push-pull outputs so it doesn't need pull resistors on its outputs. The removal of pull resistors on the inputs of the latches also allowed me to dump the voltage followers I was using in the SR latch. The analog switch is a DG201B. I should have used a DG202B because the 201 has an inverted control input. I would have preferred the more logical - or 0 for off and + for on, but that's what I had on hand.

I'll post a schematic when I have a chance to draw one up.