When I started thinking about how to use the Flip-Flap-Flops as a component in a larger system I quickly realized that they are pretty impractical if you don't have a way to reset them independently of the clock/enable line. Without an asynchronous reset there would be no convenient way to initialize the FFF on startup for instance. I started looking at how to add this functionality and it was deviously difficult because I did not want to add any more IC's to the design. Four is enough for a single trit of memory. I believe I tried and rejected nine different ideas because of various technical problems. I also worked out a couple that worked just fine but suffered from "invalid" input conditions. Analog switches are two-way devices and if you are not careful you can create a loop that feeds signals back into output pins of devices on the other side of the switch. Push-Pull outputs don't like that much and you can actually break IC's by doing this. I didn't want to settle for a solution that caused my ternary equivalent of a D Latch to have invalid input states since the fact that a D Latch doesn't have such invalid conditions is one of its hallmarks. After quite a bit of iterating on paper and in my head I finally hit on a solution that didn't require any more IC's, didn't have any invalid input conditions, and corrected the slightly annoying illogic of setting the FFF by driving the enable line low rather than high. I did need to use up the two unused comparators on the TLC3704 and add a few passives, but otherwise the design is largely the same.

Now I have a data input for the desired input state, a clock/enable line to set that state when it is driven high, and a reset line that, when driven high, will set the FFF back to 0 regardless of the state of the data line or enable line. It entirely overrides the other two inputs and does so safely. Further, the design is nicely configurable and I could also make versions that used the reset as a "preset" that would asynchronously set the device to - or +. With a little extra logic I could even have a fourth line that would allow you to choose what state the asynchronous set would be; -, 0, or +. I will post a schematic as soon as I have it drawn up.