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!Power up RESET delay

A project log for GPS Disciplined xCXO

A DIY GPS disciplined 10 MHz reference clock

nick-sayerNick Sayer 05/06/2016 at 12:552 Comments

Well, I posted about the power-up RESET delay on AVR Freaks. One thing that irks me a lot is when you post a simple question to a Q&A forum like that and instead of directly answering the question, the experts turn it into a dissertation defense. I do have to admit, though, that in this instance I had to eat a little crow.

In the end, the 5680A's frequency is not stable enough at power-up to directly clock the ATTiny. You have to wait until it achieves a physics lock before it's usable. It's not all bad news, though. The ATTiny does, of course, have an internal 8 MHz oscillator, and - this is the thing I learned - you can actually change clock sources at runtime.

So now the fuses are set for the 8 MHz oscillator at startup, and it runs that way until the !OSC_RDY line from the oscillator goes low. At that point, the clock source is changed to the external oscillator (the 5680), the USART baud rate factors are reset from 8 to 10 MHz, and the code keeps on going.

One nice side effect of this is that you can reprogram the flash or power it up for testing without the oscillator being connected.

Discussions

Yann Guidon / YGDES wrote 05/06/2016 at 13:36 point

Don't forget to disable UART before switching frequencies to avoid communication errors :-)

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Nick Sayer wrote 05/06/2016 at 13:45 point

Well, I don't disable it first, but I do wait for the output buffer to drain. I don't worry so much about the input buffer because I'm listening for NMEA sentences, and they're checksummed and dropping one at that point in the proceedings is OK.

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