So everything's working pretty well at this stage, but one thing I've had to struggle a bit with is that the firmware keeps bumping up against the limit of the ATTiny841's flash space.

Changing all of the PLL code to use fixed point rather than floating would give back some space, certainly, but it would make the code just that much more complicated and confusing.

Better would be to upgrade the controller, I think.

The nominee would be the ATMega328PB. It has 32k of flash and 2k of RAM. It also has two UARTs for the FE5680A board. Most of the extra pins wouldn't be used for anything, though. And it doesn't have the ability to switch clock sources under software control like the 841 does. What that means for the 5680A board is unclear. I went down the road of switching clock sources because the behavior of the 5680A before physics lock seemed problematic early on.

With more flash space, and with a different GPS module, the idea of sawtooth compensation for the phase discriminator becomes a possibility. GPS PPS outputs tend to have jitter because the PPS output comes from a microcontroller that's running at a certain clock frequency, and the PPS output edges are synchronized with that clock. What that means is that the edges don't have perfect granularity against GPS time, meaning it will have jitter, and since the frequency of the clock won't be precise, the jitter will have a sawtooth pattern to it as the phase drifts relative to GPS Time.

Good GPS timing modules will know the magnitude of the jitter for each PPS pulse and report that back. That means that the reported error can be removed from the phase differences detected.

That said, given the long time constants at which the PLL tends to run, it should average out for the most part.