I've come across two research papers that have caused me to rethink my previous designs. The first outlines using a single memristor to perform all logic operations via spike operations. The second outlines how a memristor with two detectable hysteresis curve can be used to store more than two values.

The paper outlining single memristor logic carries a lot of weight for me. Using the short-term memory effect of the memristor, and several other neurological processes that have been adapted electronically (blocking out noise stimuli, for example), input registered as voltage spikes will have a corresponding current spike. Like implication logic, these spike impulses work by performing a basic memristive operation to whichever state is present in the memristor's short term memory. The paper also covers reversible logic operations within one memristor, which would add another feature to this architecture. This is all well and good, but the paper is riddled with grammatical and spelling errors. Additionally, some figures are not properly captioned, casting confusion over the entire spike impulse process. Regardless, I feel that this may be an easy way to greatly simplify my prior designs. One needed feature will be converting the resulting current spikes into voltage spikes, and additionally storing this data as a different resistive state for the long term.

A second IV curve may be accessed via higher voltage and a slower sweep, as shown by the second research paper. This second state occurs with an inverted IV curve relative to the first IV curve. In addition to being proofread, this paper gives explanations as to the electrochemical interactions taking place inside of the memristor.

I am going to occupy my time with familiarizing myself with the content of these papers and trying to apply their techniques to this project. At the very least, I'll have my previous implication logic system if this ends up being a dead end.

http://gnusha.org/~nmz787/pdf/Boolean_Logic_Gates_from_a_Single_Memristor_via_Low-Level_Sequential_Logic.pdf

http://pubs.acs.org/doi/10.1021/acsnano.5b02752