For the last few weeks most of my time that I’ve spent on this project has been reading through textbooks for a Verilog refresher. While I’m making good progress through it some days I slack off completely and some days I go a bit too hard and end up burned out. So to ensure sustainable progress I’m going to whip up a dev schedule.

Currently there are three task groups that I can work on in parallel.

• FPGA HDL
  • ADC module
  • Digital module
  • IMU module
  • GPS module
  • SRAM/Interface module
  • Top level module
• XMega code
  • TBD
• Car Sim PCBs
  • Analog PCB
  • Digital PCB
  • CAN/OBD PCB

As a lot of the XMega code will depend on what I end up doing with the FPGA I’m going to somewhat ignore it for now and focus primarily on sim PBC design and the FPGA HDL. Here’s the schedule that I’m going to try to follow.

That’s all for now, I need to get back to the books.