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A project log for FPGA Doom

Porting the classic Doom engine to an FPGA-based system

matt-stockMatt Stock 06/29/2017 at 19:131 Comment

To go beyond the performance I have right now, I think I'm going to have to spend some time improving memory access. It just takes too many cycles to access memory, even with the cache helping a fair bit.

One option is to implement pipelined memory access and build a new CPU opcode that will support block memory moves. Another option would be to do another run of compacting the ISA so that there isn't as much dead space. That would have a tradeoff in decoding complexity, but I don't really think there's much of an issue there.

For the purposes of DOOM, I think the real problem though is in making the compiler smarter about using registers vs memory locations. I think that's likely the best place to start, and should mean the least amount of complexity as well. Along similar lines, I should likely try to start passing at least a few of the function parameters in registers instead of forcing it all on the stack.

Let me know your thoughts and if there's one area you find more interesting of useful than another and why.

Discussions

an00ny2k17 wrote 11/27/2017 at 08:28 point

Hi Matt, i am really interested in your project and want to try it out as a university project, however the resources available to be are BASYS3 board, and i have to do the project via a combination of MATLAB and Vivado, do you have any tips?

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