(Update: A note on the SPD EEPROMs, at the bottom)

Looking into solderless-breadboarding sdramThingZero's first prototype... apparently I'd gotten a bit side-tracked in my quest to achieve ever-increasing sample-rates (requiring a PCB) and forgot one of this project's main goals of just being a peripheral... and an approachable one, at that. (Thanks to Benchoff and a few others for the reminder).

So, the plan is to solder up some wires to a DIMM and do the rest via solderless. OK

So I dug out the old DIMMs and came across a weirdy:

This thing, quite literally, short-circuits CS0 and CS2! No joke.

OK, so... *maybe* *every* SDRAM-controller treats the chip-selects as a single unit... As in, *maybe* the only reason there are different CS-inputs, at all, is in order to reduce fan-out loading on the controller's CS-output. MAYBE. (Because, yahknow, all those address and other command pins are shared between *every* chip on the DIMM... fanout-much?).

No, this DIMM quite-literally short-circuits CS0 and CS2, checked with a multimeter, then verified on the back (unpopulated side) there is a single trace between CS1 and CS3 (which is used for the unpopulated side).

Weird. If not, frankly, potentially disastrous to some motherboards!

And... not at all compatible with sdramThing, which needs separate Chip-Selects for the "free-runner" and the "side-kick."

And... This leads me to check my remaining SDRAM DIMM stock for other such oddities... Here's another DIMM that's a bit strange; this guy has 16 chips (8 on each side) but only makes use of CS0 and CS2, doesn't use CS1 and CS3, which are, again, usually for the other "side".

These guys don't match the specs in that intel document, at all.

Well, actually, I've yet to check, maybe this 16-chipper is actually populated with 4-bit chips, rather'n 8-bit... (hmm).

So, then... sdramThingZero might have to be a bit specific regarding *which types* of SDRAM it'll work with... which may boil down to getting out your multimeter and verifying the layout...

Yay Standards!

An alternative that would avoid being thwarted by those oddities... use two separate (matched) DIMMs... oy.

SDRAM DIMMs have SPD (Serial Presence Detect) EEPROMs built-in... These guys can help give an idea of the layout (but, again, might not be *entirely* truthful).

I'll maybe give more info on *reading* that SPD EEPROM, e.g. via a i2c-tiny-usb... (or maybe even connect it to your computer's VGA/EDID port).

But I wanted to make note, first:

NOTE: Make sure your I2C reader uses 3.3V!

Even though many/most I2C EEPROMs can handle a 5V supply, some DIMM-manufacturers don't go to the trouble of isolating the SPD-VCC from the SDRAM-VCC. So, if you supply 5V to the SPD VCC pin, it might very-well power the entire DIMM (including the SDRAM chips, very-likely rated only for 3.3V) with 5V.

(On that note, consider that by powering the SPD EEPROM, you might well be *also* powering up to 16 other chips... so you might need some current).

(I've thrown a file about decoding the SPD parameters in the files-section)