Bus-Hold, briefly: (see, e.g. TI's explanation http://www.ti.com/lit/an/scla015/scla015.pdf)

For a system where several devices are connected to a bus, there may be times when *none* of the devices are selected to output a voltage onto that bus.

In which case, the input-voltage to all the devices will "float", and, briefly, that's not good.

In one case, *both* transistors (the N and P-channel mosfets) will be active at the same time, causing somewhat-significant power-consumption. (did I see 5mA per input?!)

In another case, the input-circuitry will *oscillate*... And that causes even higher current-draw, but also injects a bunch of noise into the entire system... (decoupling capacitors?)

Bad idea, probably, to allow this to happen... but is it really *bad* per-se...? Are there cases where it doesn't matter, much? I'm not too worried about power-consumption, as a hobbiest trying to build something that works. And, maybe, decoupling-capacitors are good-'nough to prevent oscillation from escaping from an otherwise *deselected* (non-outputting) chip into the other circuitry that is functioning...

They've already created ICs that have "bus-hold" circuits built-in. These circuits basically take the input, feed it through a buffer, then feed that output back to the input with a resistor. (side-note on how that's quite similar to my use of resistors in signal-routing, and as well for my original design of the trigger-handler latch).

Then, why not just use these chips that have bus-hold, and call it a day...? They don't cost much more, (in fact, at my supplier right now, they're cheaper).

They do, however, take a (tiny) bit of extra input-current... worst-case nearly half a milliamp, *each*... during switching.

But that application-note shows a good example... what when you've got 8 devices on the same bus, all with bus-hold on their inputs.... Well, most devices are capable of switching 24mA, these days... so "negligible effect"-ish... great!

(Still, does that make sense when talking about .5mA * 8 = 4mA, AND they actually discussed devices with 4mA outputs? Huh... suddenly our switching-speed is slowed, dramatically, no? While not only dealing with that 4mA of load, we've also got to overcome input-capacitances... huh.).

But then the next example is the kicker...

What happens when you've got pull-up/pull-down resistors on your bus...? Read that section (or skim)... Basically the jist is, their calculations show that where once a 10-100k pull-up/down resistor would've worked, now you need less than 3k, and that's only with *one* bus-hold device connected!

(The weird thing is, some of these manufacturers give the *same* datasheet for both LVT and LVTH, surely these numbers (input characteristics) are quite different for these two. And I'm almost certain they showed only one set of numbers. Huh.)

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One more time... whereas previously a 100k resistor would've been enough for a pull-up, now we need less than 3k. That's pretty significant. Nowhere *near* "negligible."

Which means I should probably reread that section and understand/do that math myself. And maybe look into the other bus-hold topologies (e.g. those from the NXP sheet: http://www.nxp.com/documents/application_note/AN2022.pdf)

And... maybe not assume that just because they have the same family-designation means they work the same (74LVT[H] from e.g. NXP vs. TI).

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Because, in part.... you may recall from previous logs, I've been trying to get away with using resistors to direct signals back across the latches (in the reverse-direction), rather than using buffers with output-enables (requiring more control-signals).

Whelp, those resistors, essentially, look like pull-up/pull-down resistors (their polarity just happens to be driven by a device on the bus). So, I don't know how much smaller they might need to be... I was already thinking about something along the lines of 470ohms (since I happen to have a *lot* of those resistor-networks)... but, yahknow, that might have to be decreased even further if my system has a lot of bus-hold inputs. Something to think about, and not something I really have the brain-power *to* think-through in the next few days...

So, my original order, before I even began reading-up on bus-hold, was going to be for 10 of each: LVT without bus-hold, and LVTH with... and I'd figure it out when I had the parts... I guess that's what I'll do. Unfortunately, the supplier doesn't have the LVT in SOIC, and the LVTH in SOIC is a min-quantity of 25... So, first, I thought maybe getting *all* with bus-hold (in the much-more-prototype-friendly SOIC) would be acceptable, with a bit more reading-up... but I guess I'mma stick with the original 10/10 order of TSSOPs (oy).

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And, all this leads to the intricacies of trying to make this thing capable of 133MS/s... Again, we've already got 30MS/s with some decades-old parts I had lying around... Surely more than useful to build over a weekend... But if you want 133, you're gonna need a well-thought-out layout (PCB) and specific parts, or I'm going to have to design it with these sorts of things in mind.