My goal for this project was to visualise how a IC my be working from the inside. Oke: lets build a Tranisistor CPU. But building a CPU is hard. Way to hard for me. Thats why I built a UART reciever. Its still complicated and abstract, but it is understandable. I learned a lot while building this and I hope you can learn something here too :)
All details can be found in my written work, but to summarize ot shortly (i dont want to write the whole thing in english again hahaha):
UART is a serial communication protocol, used widely in electronics (it is the connection inbetween your Arduino an the USB bus of your computer, for example).
This is how it works:
Every UART device has a TX and a RX pin. The TX pin transmits data, and the RX pin recieves data.
TX ---> RX
RX <--- TX
So we need 2 wires to connect 2 UART devices (+ Ground).
There is no clk signal wire, so both devices need to agree on the same baud rate (= bit rate or bit/s) which is often 9600 baud.
So for our circuit to work, we need a internal Clock generater, but that comes later.
First of all: one UART Message containes
1 Start bit (always 0 (LOW)) which marks the beginning of a UART message.
5-9 Data Bits (but 8 bIts is normally used)
0-1 Parity Bits to perform a parity check, which can detect one (1) ! flipped Bit or fault in the recieved data (this is normally not used, but i implemented it to make my project more interesting)
1-2 Stop Bits, to mark the end of the Message
My Configuartion: 1 Start Bit, 8 Data Bits, 1 Parity Bit, 1 Stop Bit = 11 Bit long message.
When there is no information beeing send over the UART line, then it stays always HIGH which is often 5V in the microcontroller world.
Ok. To recieve a UART message, we need to build a circuit called a Shift Register.
A shift register is build from a lot of NAND GATE Flipflops, which are chained together and can pick bits and move it through the shift register. For that to work, it needs a clock signal.
But we cant just slap a clock signal all the time on it. The clock signal functions as the activation signal, so the shift register will just throw all the bits out, if we keep it running all the time. Thats why a activation circuit is needed, which lets the clock signal pass through it to the Shift register, when there is a UART message incoming. This circuit will also deactivate the clock Signals when the Message is recieved, so it can be stored further.
The generated clock signal gets split up in two inverted clock signals (CLK+ and CLK-), which have to pass trough the Enable Circuit to activate the shift register (Enable+ and Enable-). This happens when Enable Full is HIGH, which is controlled by the Trigger Circuit Enable Setting Bit Flipflop (sry for those long names haha). This flipflop can either be manually controlled by two pushbuttons, or, more convenient, is controlled automaticly. When there is a message incoming, the start bit (from the RX IN) will SET the Flipflop, which makes Enable full go HIGH. All the incoming Bits from the RX Line will now be stored and shifted in the shift Register, including the Start bit. After 10 clock cycles, the Start bit (LOW) will have passed through the shift register and will be inverted to a HIGH on the Reset Enable line. this RESETs the Flipflop. At the same time, the Stop bit will be on the RX line, which prevents the Flipflop from SET-ing again immediately.
With this setup, it is possible to:
1: activate and deactivate the shift register
2: deactivate the shift register without using a counter circuit of some sort. The shift register acts as the counter by itself. This way, I was able to save a lot of work and time.
3: activating and deactivating the shift register manually for troubleshoot purposes (which wasn't needet as much, but im still glad I implemeted it)
Sooo, i still havent talked about the clock signal. how is ist generated. Well it is...
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Great project! Quite probably this was exactly the way such circuits were implemented before first UART/ACIA chips appeared in early 1970. Btw, check out my approach to the same problem, which does not use the usual T/2 trigger logic at the start bit: https://hackaday.io/project/181664-intel-hex-files-for-fpgas-no-embedded-cpus/log/197810-ser2par-a-novel-uart-receiver-delay-line-approach