Suppressing the INC L instruction can be accomplished by setting D5 = D4 or RTS.

Initialising HL and A can be done using POP HL and POP AF, since the result of the ‘dummy’ memory reads performed during execution of these depend only on the value of SP (which is initialised to 0000h at reset).

The following sequence will do it (I’ve put the hex and binary code for each instruction next to the instruction). The 3rd instruction in this sequence was chosen to make the data lines a simple function of the address lines. Because HL is initialised before LD H,(HL) is executed, it will set H to a function of HL - i.e. a constant value.

E1 11100001 POP HL
F1 11110001 POP AF
66 01100110 LD H,(HL)
76 01110110 HALT

 You can see that each bit here is either constant or equal to A0 or A1 or their negation:

D7=/A1

D6=1

D5=1

D4=A0

D3=0

D2=A1

D1=A1

D0=/A1

So we can initialise A and HL by using this setup first, then manually switching to the setup described in the previous log entry after the HALT instruction is executed but before the first NMI. I think that this switchover can be done using a single 4PDT switch.

Since the ‘or’s appearing in the data line expressions in the previous log entry can be implemented using diodes, I think that this bootstrapping scheme can be made without any additional ICs, so this ROMless bootstrapping scheme will use only 3 ICs in total: A 7400 quad 2-input NAND gate which is used to generate the clock signal and to invert A0 and A1. A static memory chip (I’m going to use an old 6116 2Kx8 RAM because I have a lot of old ones in my parts drawers), and the Z80 itself.

I will draw a schematic when time permits, and also try to describe the scheme in more detail, because I don’t think I’ve clearly expressed the idea.

It’s possible that I’ve made some mistake in thinking about this, but hopefully any mistakes will come to light in the course of writing it down in more detail.